Method of forming a thin substrate chip scale package device and structure

ABSTRACT

In one embodiment, a method for forming an electronic package structure includes providing a single unit leadframe having first terminals on a first or top surface. An electronic device is attached to the single unit leadframe and electrically connected to the first terminals. The leadframe, first terminals, and the electronic device are encapsulated with an encapsulating material. Second terminals are then formed by removing portions of a second or bottom surface of the leadframe. In one embodiment, the method can be used to fabricate a thin substrate chip scale package (“tsCSP”) type structure.

CROSS REFERENCE TO RELATED APPLICATIONS

The present application is a continuation application of U.S. Ser. No. 12/750,022 filed on Jan. 25, 2013, which claims priority to Korean Patent Application No. 10-2012-0040673 filed on Apr. 19, 2012, both of which are expressly incorporated by reference herein in their entirety to provide continuity of disclosure.

BACKGROUND

The present invention relates to electronic devices, and more specifically to electronic device package structures and methods of fabricating the same.

Electronic devices, such as semiconductor dies are conventionally enclosed in plastic packages that protect the semiconductor die from hostile environments and that enable electrical interconnection between the semiconductor die and a next level of assembly, such as a printed circuit board (PCB) or motherboard. The elements of a typical electronic package include a conductive leadframe or substrate, an integrated circuit or semiconductor die, conductive structures, such as bond wires or solder balls that electrically connect pads on the semiconductor die to individual leads of the leadframe or substrate; and a hard plastic encapsulant material that covers the other components and forms an exterior of the semiconductor package commonly referred to as the package body. Portions of the individual leads can be exposed to electrically connect the package to the next level assembly.

Chip scale packaging (“CSP”) is one packaging technique currently used to support end-user demands for increased integration and increased functionality coupled with demands for thinner and smaller footprint packages. One type of CSP device is referred to as a thin substrate CSP device or tsCSP device. FIGS. 3A to 3E show cross-sectional views of a known manufacturing process for fabricating tsCSP style devices.

As shown in FIG. 3A, a cavity 2 is formed in a dual stepped manner on a bottom surface of a leadframe 1. Next, cavity 2 of leadframe 1 is filled with a dielectric material 3 so that a bottom surface of dielectric material 3 is coplanar with the bottom surface of leadframe 1 as shown in FIG. 3B.

Subsequently, an etching process is used to form a desired pattern on the top surface of leadframe 1, as shown in FIG. 3C. During the etching process, portions of the top and side surfaces of leadframe 1 are removed to form multiple independent terminals 4 having a predetermined pattern or array. Dielectric material 3 insulates the independent terminals 4 from each other.

Next, as shown in FIG. 3D, bond pads on a semiconductor chip 5 are attached to independent terminals 4 on the top surface of leadframe 1 using conductive bumps 6. Thereafter, the structure is placed into a molding apparatus and the structure is molded with a molding compound resin 7 as shown in FIG. 3E. Molding compound resin 7 encapsulates semiconductor chip 5 as well as the top surface of leadframe 1. In the completed tsCSP device, independent terminals 4 are exposed through a bottom surface thereof to be mounted to a next level of assembly.

The conventional tsCSP fabrication method of 3A-E has several disadvantages. First, the very thin leadframe is very difficult to handle during the etching process and the independent terminals are left unsupported except for the insulation material, which has been found to be very limited and ineffective. The handling problems also affect the step of mounting the semiconductor chip to the independent terminals and the external forces have been found to cause breakage and other failure mechanisms.

Second, because the independent terminals, the insulating material, and the semiconductor chip have different thermal expansion coefficients, warpage has been found to occur during the molding step. This has resulted in delamination, which can occur, for example, at interfaces between the independent terminals and the insulating material.

Third, in the conventional process the independent terminals are etched before the steps of mounting the semiconductor chip and molding the structure. External forces can cause the location of the independent terminals to deviate from desired positions making alignment and placement of the semiconductor chip onto the independent terminals difficult. This can detrimentally impact process cycle time and device reliability.

Accordingly, it is desirable to have a structure and method for forming electronic device package structures including CSP structures and tsCSP structures that address the issues set forth above as well as others.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A to 1H illustrate cross-sectional views an electronic package according to an embodiment of the present invention at various stages of fabrication;

FIGS. 2A to 2I illustrates cross-sectional views of an electronic package according to another embodiment of the present invention at various stages of fabrication; and

FIGS. 3A to 3E show cross-sectional views of a related thin substrate chip scale package structure at sequential stages of manufacture.

For simplicity and clarity of the illustration, elements in the figures are not necessarily drawn to scale, and the same reference numbers in different figures denote the same elements. Additionally, descriptions and details of well-known steps and elements are omitted for simplicity of the description.

DETAILED DESCRIPTION OF THE DRAWINGS

FIGS. 1A to 1H illustrate cross-sectional views of an electronic package structure 100, such as a semiconductor package at various stages of fabrication in accordance with a first embodiment. In one embodiment, electronic package structure 100 includes a single unit leadframe 10 having a predetermined thickness as illustrated in FIG. 1A. In one embodiment, leadframe 10 can be a conductive material such as a metal, a metal alloy, a material electroplated with a conductive material, or similar material as known by one of ordinary skill in the art.

Portions of a top surface of single unit leadframe 10 are removed to form a plurality of terminals or terminals 12 that have a desired pattern and that protrude upward from remaining portions of single unit leadframe 10 as illustrated in FIG. 1B. In one embodiment, a first or top surface of single unit leadframe 10 is covered by a mask, such as photoresist, and portions of the top surface are etched away in etch solution thereby forming terminals 12 having the desired pattern and protruding from the top surface of single unit leadframe 10.

In one embodiment, an electronic device such as, a semiconductor chip 14 is attached to terminals 12, as illustrated in FIG. 1C. In accordance with one embodiment, conductive structures or conductive input/output terminals 22 electrically connect bond pads on semiconductor chip 14 to terminals 12. In one embodiment, input/output terminals 22 are configured as conductive bumps 22 a. In one embodiment, conductive bumps 22 a allow the bonding pads of semiconductor chip 14 to be conductively attached or welded to each of the respective terminals 12 of single unit leadframe 10 by a reflow process.

FIG. 1D illustrates a cross-sectional view of electronic package structure 100 after further processing. In one embodiment, a molding compound resin or encapsulating layer 16 can be molded throughout the top surface of single unit leadframe 10 to encapsulate semiconductor chip 14 and conductive input/output members 22. In one embodiment, molding compound resin 16 completely covers side surfaces 122 of terminals 12 as illustrated in FIG. 1D, which is different than the previous device shown in FIG. 3E where resin layer 7 can only partially cover the side surfaces terminals 4 because other portions of the side surfaces of terminals 4 are covered by dielectric material 3. Stated another way, side surfaces 122 of terminals 12 are devoid of an insulating layer as illustrated in FIG. 1D.

In contrast to previous methods where the separated terminals are formed by etching the leadframe before mounting and encapsulating the semiconductor chip, the mounting of semiconductor chip 14 and the molding by molding compound resin 16 are performed without separating single unit lead frame 10 into independent terminals, which improves the handling efficiency between processing steps. Also, the method in accordance with the present embodiment minimizes the effects caused by the separated terminals deviating from desired locations before the semiconductor chip mounting step as found in the previous method. In addition, because terminals 12 of single unit leadframe 10 are simultaneously connected to semiconductor chip 14 and still connected together during the molding step, the previous issues of interface delamination due to warpage can be reduced.

FIGS. 1E to 1H illustrate cross-sectional views of electronic package structure 100 after further processing of single unit leadframe 10 to form independent terminals or terminals 20. In one embodiment, portions of a second or bottom surface single unit leadframe 10 can be removed to form terminals 20 using photoresist and etch process. In one embodiment, a layer of photoresist 18 is attached to or formed on the bottom surface of single unit leadframe 10 as illustrated in FIG. 1E.

Subsequently, photoresist 18 can be exposed and developed leaving a desired pattern protecting or covering portions of the bottom surface of single unit leadframe 10 where terminals 20 are to be formed, as illustrated in FIG. 1F. This step leaves portions of the bottom surface of single unit leadframe 10 exposed, and these exposed portions can then be removed or etched away to form independent terminals 20, as illustrated in FIG. 1G. Photoresist layer 18 can then be removed. In the present embodiment, independent terminals 20 are formed after the molding. Independent terminals 20 are configured for attachment to a next level of assembly. In one embodiment, the removal step to form independent terminals 20 can expose portions of terminals 12 through molding compound resin 16, as illustrated in FIG. 1G.

In an optional step, an insulating material 24, such as an epoxy resin, a solder resist or a molding compound resin, can be placed or filled in spaces formed between independent terminals 20 as illustrated in FIG. 1H. This step can be used to planarize the bottom surface of electronic package structure 100 and to further insulate independent terminals 20 from each other. In this configuration, independent terminals 20 can be attached to a next level of assembly using, for example, solder balls or solder bumps.

FIGS. 2A to 2I are cross-sectional views of an electronic package structure 200, such as a semiconductor package at various stages of fabrication in accordance with another embodiment. In one embodiment, electronic package structure 200 has a configuration similar to electronic package structure 100 and is fabricated in similar manner. However, electronic package structure 200 is different than electronic package structure 100 because conductive wires 22 b are used as conductive input/output members 22 connecting semiconductor chip 14 to single unit leadframe 10.

In one embodiment, electronic package structure 200 includes single unit leadframe 10 having a predetermined thickness as illustrated in FIG. 2A. Terminals 12 can formed to protrude from the top surface of single unit leadframe as illustrated in FIG. 2B and further described in conjunction with FIG. 1B. In accordance with the present embodiment, bonding layers or plated layers 26 can be formed on some of terminals, as illustrated in FIG. 2C to facilitate the using of bonding wires 22 b. In one embodiment, terminals 12 can be made of copper, and layers of gold (Au) and nickel (Ni) can be sequentially formed or plated onto surfaces of terminals 12 to form bonding layers 26. In another embodiment, layer of silver (Ag) can formed or plated onto surfaces of terminal 12 to form bonding layers 26.

Subsequently, semiconductor chip 14 is attached to single unit leadframe 10 using, for example, an adhesive material 33, and conductive wires 22 b are attached to bonding pads on semiconductor chip 14 to bonding layers 26 on terminals 12, as illustrated in FIG. 2D. Molding compound resin 16 is then molded throughout the top surface of single unit leadframe 10 to encapsulate semiconductor chip 14 and conductive wire 22 b, as illustrated in FIG. 2E.

Similar to the method used to form electronic package structure 100, the method in accordance with the present embodiment includes the steps of mounting of the semiconductor chip 14 and molding by molding compound resin 16 before single unit leadframe 10 is separated into independent terminals 20. Thus, handling efficiency between processing steps is improved. Also, the method in accordance with the present embodiment minimizes the effects caused by the separated terminals deviating from desired locations before the semiconductor chip mounting step as found in the previous method. In addition, because terminals 12 of single unit leadframe 10 are simultaneously connected to semiconductor chip 14 and are still connected together during the molding step, the previous issues of interface delamination due to warpage can be reduced.

FIGS. 2F to 2I illustrate cross-sectional views of electronic package structure 200 after further processing of single unit leadframe 10 to form independent terminals or terminals 12. In one embodiment, terminals 12 are formed in electronic package 200 in a similar manner, as described in conjunction with FIGS. 1E to 1H.

From all of the foregoing, one skilled in the art can determine that according to one embodiment, a method for forming an electronic package structure (for example, elements 100, 200) includes providing a single unit leadframe (for example, element 10) having first terminals (for example, element 12) protruding in a predetermined array on a first surface. The method includes attaching an electronic chip (for example, element 14) to the first surface. The method includes forming an encapsulating layer (for example, element 16) on the first surface to encapsulate the electronic chip. The method includes removing portions of a second surface of the single unit leadframe to form independent terminals (for example, element 20) on the second surface.

Those skilled in the art will also appreciate that, according to another embodiment, a method of forming a semiconductor package structure (for example, elements 100, 200) includes comprising providing a single unit leadframe (for example, element 10) having first terminals (for example, element 12) protruding from a first surface. The method includes attaching a semiconductor chip (for example, element 14) to the first terminals. The method includes encapsulating the semiconductor chip and the first surface with encapsulating layer (for example, element 16). The method includes thereafter removing portions of a second surface of the single unit leadframe opposite to the first surface to form independent terminals (for example, elements 20) electrically coupled to the first terminals.

Those skilled in the art will also appreciate that according to a further embodiment, an electronic package structure (for example, elements 100, 200) a leadframe (for example, element 10) having first terminals (for example element 12) defining a first surface and second terminals defining a second surface, wherein the first terminals and the second terminals are connected together in a predetermined pattern. An electronic chip (for example, element 14) is attached to the first surface and electrically coupled to the first terminals (for example, elements 22, 22 a, 22 b). An encapsulating layer (for example, element 16) covers the electronic chip and the first terminals including side surfaces (for example, element 120) thereof.

In view of all the above, it is evident that a novel method and structure is disclosed. Included, among other features, is a single unit leadframe having first terminals formed to protrude from a first surface of the single unit leadframe. An electronic chip is then attached to the single unit leadframe and electrically connected to the first terminals. The electronic chip and first terminals are covered with an encapsulant. Portions of the second surface of the single unit leadframe are then removed to form independent terminals, which are electrically connected to the first terminals. The method and structure reduce handling problems associated with prior methods. The method and structure also reduce alignment problems during the chip attachment process associated with prior methods, and further reduce problems associated with delamination between the encapsulating layer and the leadframe.

While the subject matter of the invention is described with specific preferred embodiments and example embodiments, the foregoing drawings and descriptions thereof depict only typical embodiments of the subject matter, and are not therefore to be considered limiting of its scope. It is evident that many alternatives and variations will be apparent to those skilled in the art. For example, the subject matter has been described for semiconductor devices; however the method and structure is directly applicable to other electronic devices, such as optoelectronic devices, sensor devices, imaging devices, solar cells, medical devices, and other devices configured for and/or benefited by package structures.

As the claims hereinafter reflect, inventive aspects may lie in less than all features of a single foregoing disclosed embodiment. Thus, the hereinafter expressed claims are hereby expressly incorporated into this Detailed Description of the Drawings, with each claim standing on its own as a separate embodiment of the invention. Furthermore, while some embodiments described herein include some but not other features included in other embodiments, combinations of features of different embodiments are meant to be within the scope of the invention, and form different embodiments, as would be understood by those skilled in the art. 

What is claimed is: 1-20. (canceled)
 21. A method for forming an electronic package structure comprising: providing a single unit leadframe having a first surface with first terminals protruding in a first predetermined array, wherein the first terminals are separated by a plurality of grooves, and wherein the single unit leadframe has a second surface opposite to the first surface, and wherein the second surface is a substantially planar surface; electrically connecting an electronic chip to the first terminals; forming an encapsulating layer on the first surface to encapsulate the electronic chip and at least some of the plurality of grooves; and thereafter selectively removing portions of the second surface of the single unit to form second terminals in a second predetermined array and coupled to the first terminals, wherein the first predetermined array is different than the second predetermined array.
 22. The method of claim 21, wherein electrically connecting the electronic chip comprises attaching the electronic chip to the first terminals using conductive solder balls.
 23. The method of claim 21, wherein attaching the electronic chip comprises: placing an adhesive within a first groove, wherein the adhesive is absent from a second groove; attaching the electronic chip to one or more of the first terminals using the adhesive, wherein the electronic chip overlaps the first groove; and attaching conductive structures to bond pads on the electronic chip and to other first terminals, and wherein forming the encapsulating layer includes forming the encapsulating layer in the second groove but not the first groove.
 24. The method of claim 23, wherein attaching the conductive structures includes attaching conductive wires.
 25. The method of claim 21, wherein forming the encapsulating layer includes forming the encapsulating layer to completely cover side surfaces of the first terminals.
 26. The method of claim 21, wherein electrically connecting the electronic chip comprises electrically connecting a semiconductor chip.
 27. The method of claim 21, wherein selectively removing portions of the second surface comprises: forming a photoresist layer on the second surface; patterning the photoresist layer to expose portions of the second surface; and etching the exposed portions of the second surface to form a non-planar second surface.
 28. The method of claim 21 further comprising forming an insulating layer in spaces between the second terminals.
 29. The method of claim 21, wherein providing the single unit leadframe comprises: forming a patterned mask on the first surface of the single unit leadframe but not the second surface; and removing exposed portions of first surface to form the first terminals without forming patterned features in the second surface.
 30. The method of claim 21, wherein providing the single unit leadframe comprises providing the second surface absent any patterned features extending inward from the second surface at least where the second surface and the first terminals overlap.
 31. The method of claim 21, wherein providing the single unit leadframe comprises providing a second surface that is non-selectively etched.
 32. A method of forming a semiconductor package structure comprising: providing a single unit leadframe having a first surface defining first terminals in a first predetermined array, wherein the first terminals are separated by a plurality of gaps, and wherein the single unit leadframe has a second surface opposite to the first surface that is substantially planar; electrically connecting a semiconductor chip to the first terminals; forming an encapsulating layer that encapsulates the semiconductor chip, the first terminals, at least some of the plurality of gaps, and at least a portion of the first surface; and thereafter selectively removing portions of the second surface of the single unit leadframe to form second terminals in a second predetermined array, wherein the first predetermined array has a different pattern than the second predetermined array.
 33. The method of claim 32, wherein providing the single unit leadframe comprises providing the second surface free from any patterned features at least where the second surface and the first terminals overlap.
 34. The method of claim 32, providing the single unit leadframe comprises: forming a patterned mask on the first surface of the single unit leadframe but not the second surface; and removing exposed portions of first surface to form the first terminals without forming patterned features in the second surface.
 35. The method of claim 32, wherein electrically connecting the semiconductor chip comprises: placing an adhesive within a first gap, wherein the adhesive is absent from a second gap; attaching the semiconductor chip to one or more of the first terminals using the adhesive, wherein the semiconductor chip overlaps the first gap; and attaching conductive structures to bond pads on the semiconductor chip and to other first terminals, and wherein forming the encapsulating layer includes forming the encapsulating layer in the second gap but not the first gap.
 36. The method of claim 32, wherein electrically connecting the semiconductor chip comprises electrically connecting both opposing major surfaces of the semiconductor chip to the first terminals.
 37. The method of claim 32, wherein electrically connecting the semiconductor chip includes directly attaching bond pads on the semiconductor chip to the first terminals with solder structures in a flip-chip configuration.
 38. The method of claim 32, wherein providing the single unit leadframe comprises providing a second surface that is non-selectively etched.
 39. The method of claim 32 further comprising forming an insulating layer in spaces between the second terminals.
 40. A method for forming a thin substrate chip scale packaged electronic device comprising: providing a leadframe comprising a conductive material and having a plurality of first terminal portions protruding from a first surface in a first predetermined pattern, the first predetermined pattern including a plurality of grooves between the first terminal portions, the leadframe further comprising a generally planar second surface that is non-etched in selective manner, wherein the generally planar second surface is opposite to the first surface; electrically coupling an electronic device to the plurality of first terminal portions; forming a mold layer covering the electronic device and the plurality of grooves; and thereafter selectively etching the second surface in a second predetermined pattern to expose portions of the molded encapsulating layer and to provide a plurality of second terminal portions connected to the plurality of first terminal portions with spaces between the plurality of second terminal portions, wherein the second predetermined pattern is different than the first predetermined pattern; and providing an insulating layer within the spaces, wherein the insulating layer adjoins the molded encapsulating layer. 